1. Field of the Invention
The present invention relates generally to a semiconductor device having mutually different two gate threshold voltages and a fabrication process thereof. More specifically, the invention relates to a compound semiconductor device including two kinds of field effect transistors (FET), an enhancement type transistor (hereinafter referred to as E-type FET or E-type FET region) and a depletion type transistor (hereinafter referred to as D-type FET or D-type FET region), and a fabrication process therefor.
2. Description of the Related Art
According to the trend for faster computer speeds in recent years, there is a strong demand for higher speed and lower power consumption of an integrated circuit device. Compound semiconductor devices, such as gallium arsenide (GaAs) semiconductor and the like, have greater electron mobility in comparison with silicon (Si) semiconductor devices. For this reason, application of the compound semiconductor devices for compact computers are greatly expected.
When an integrated circuit device is constructed with compound semiconductors, inverter circuits, and direct couple FET logic (DCFL) circuits, as basic elements are frequently used. In such a case, an E-type FET is used as a driving element and a D-type FET is used as a load element. A threshold voltage Vth of the E-type and D-type FETs is determined by a layer thickness of a carrier supply layer or a threshold voltage control layer.
As an effective method for simultaneously forming the E-type FET and the D-type FET on the same substrate, there has been known a selective etching method by providing an etching stop layer in an epitaxially grown crystal layer to control an etching stop position.
For example, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. Showa 60-231368 and Japanese Unexamined Patent Publication No. Heisei 2-148740. Since the latter is an improvement of the for with reference to FIG. 1, taking the latter as an example.
A semiconductor device shown in FIG. 1 is fabricated by growing an undoped GaAs layer 203 to a thickness of 500 nm, an n-type AlGaAs layer 204 to a thickness of 30 nm, a fourth n-type GaAs layer 205a to a thickness of 10 nm serving as a threshold voltage control layer in a D-type FET, an n-type AlGaAs layer 206a to a thickness of 5 nm serving as a third etching stopper layer, a third n-type GaAs layer 205b to a thickness of 15 nm serving as a contact layer, an n-type AlGaAs layer 206b to a thickness of 5 nm serving as a second etching stopper layer, a second n-type GaAs layer 207 to a thickness of 60 nm serving as a contact layer, and an n-type AlGaAs layer 208 to a thickness of 5 nm serving as a first etching stopper layer and a first n-type GaAs layer 209 to a thickness of 40 nm serving as a contact layer on a semi-insulative GaAs substrate 201 in sequential order. A Schottky gate electrode of the E-type FET is in contact with the n-type AlGaAs layer 204 as the electron supply layer, and a Schottky gate electrode of the D-type FET is in contact with the n-type AlGaAs layer 206a serving as the third etching stopper layer.
A fabrication process of the compound semiconductor device shown in FIG. 1 is illustrated in FIGS. 2A to 2E in sequential order of process steps. At first, as shown in FIG. 2A, the undoped GaAs layer 203 serving as the channel layer, the n-type AlGaAs layer 204 serving as the electron supply layer, the fourth n-type GaAs layer 205a serving as the threshold voltage control layer in a D-type FET, the n-type AlGaAs layer 206a serving as the third etching stopper layer, the third n-type GaAs layer 205b serving as the contact layer, the n-type AlGaAs layer 206b serving as the second etching stopper layer, the second n-type GaAs layer 207 serving as a contact layer, the n-type AlGaAs layer 208 serving as the first etching stopper layer and the first n-type GaAs layer 209 serving as a contact layer on a semi-insulative GaAs substrate 201 are grown in sequential order by molecular beam epitaxy method (MBE method) or metal organic chemical vapor deposition (MOCVD) method. Subsequently, by way of mesa etching or ion implantation, isolation is performed. Etching is performed for the n-type GaAs layer 209 and the n-type AlGaAs layer 208 in the E-type FET region using a photo resist as a mask to form a recess 222.
Next, as shown in FIG. 2B, an insulation layer 210 with a thickness of 30 nm is grown over the entire surface. Then, using a photo resist as a mask, an opening is formed in the insulation layer 210. Then, using a lift off method, source electrodes 217 and 219 and drain electrodes 218 and 220 are formed as ohmic contacts.
Next, as shown in FIG. 2C, in order to form a gate electrode in each of the E-type and D-type FET regions, gate openings 213 and 214 are formed in the insulation layer 210 using a photo resist layer 211 as a mask using, e.g. by employing lithography and etching technologies. Isotropic etching is performed for respective n-type GaAs layers of respective E-type and D-type FET regions by way of RIE employing CC1.sub.2 F.sub.2 gas. At this time, the n-type AlGaAs layers below the n-type GaAs layers 207 and 209 (i.e. the second etching stopper layer 206b and the first etching stopper layer 208) serve as etching stoppers.
Next, as shown in FIG. 2D, using a hydrofluoric acid type etching liquid, the n-type AlGaAs layers 206b and 208 as the etching stopper layers are selectively etched to expose the n-type GaAs layers 205b and 207, respectively, placed therebelow. Subsequently, isotropic selective etching of the n-type GaAs layers 205b and 207 is performed by RIE employing CC1.sub.2 F.sub.2 gas for exposing the n-type AlGaAs layers 206a and 206b located therebelow. Then, similar to the process set forth above, the n-type AlGaAs layers 206a and 206b as etching stopper layers are selectively etched by hydrofluoric acid type etching liquid to expose the n-type GaAs layers 205a and 205b located therebelow. Also, under a condition of low pressure and high self-bias voltage, anisotropic selective etching for the n-type GaAs layers 205a and 205b is performed by RIE employing CC1.sub.2 F.sub.2 gas to expose the n-type AlGaAs layer 204 and 206a.
Thereafter, as shown in FIG. 2E, Schottky junction type gate electrodes 215 and 216 are formed in respective gate openings 213 and 214 by aluminum or the like to complete the E-type and D-type FETs.
On the other hand, Japanese Unexamined Patent Publication No. Heisei 8-116034 discloses the prior art as illustrated in FIG. 3.
The semiconductor device of FIG. 3 has an undoped GaAs layer 302 with a thickness of 400 nm serving as a buffer layer, an undoped InGaAs layer with 303 with a thickness of 15 nm serving as a channel layer, an n-type AlGaAs layer 304 with a thickness of 30 nm serving as an electron supply layer, a second n-type GaAs layer 307 with a thickness of 4 nm serving as a threshold voltage control layer, an n-type AlGaAs layer 308 with a thickness of 3 nm serving as an etching stopper layer, and a first n-type GaAs layer 309 with a thickness of 100 nm serving as a contact layer are grown on a semi-insulative GaAs substrate 301 in sequential order. A Schottky gate electrode of the E-type FET is in contact with the n-type AlGaAs layer 304 as the electron supply layer and a Schottky gate electrode of the D-type FET is in contact with the n-type AlGaAs layer 308 as the etching stopper.
One example of the fabrication process of the semiconductor device shown in FIG. 3 will be discussed hereinafter with reference to FIGS. 4A to 4F.
At first, as shown in FIG. 4A, the undoped GaAs layer 302 as the buffer layer, the undoped InGaAs layer 303 as the channel layer, the n-type AlGaAs layer 304 as the electron supply layer, the second n-type GaAs layer 307 as the threshold voltage control layer, the n-type AlGaAs layer 308 as the etching stopper layer, and the first-n-type GaAs layer 309 as the contact layer grown on the semi-insulative GaAs substrate 301 are grown in sequential order. Then, isolation is performed by ion implantation.
Next, as shown in FIG. 4B, after growth of an insulation layer 310 of SiO.sub.2 over the entire surface of the substrate, gate openings 313 and 314 are formed by lithography and RIE technology. After removal of a photo resist, selective dry etching is performed for the first n-type GaAs layer 309 relative to the n-type AlGaAs layer 308, using the insulation layer 310 as a mask.
Then, as shown in FIG. 4C, an insulation layer is grown on the surface. Thereafter, anisotropic etching is performed by RIE to form a side wall insulation layer 321.
Next, as shown in FIG. 4D, the gate opening portion 314 of the D-type FET region is covered with a photo resist layer 311b. After removing the n-type AlGaAs layer 308 exposed through the gate opening portion 313 of the E-type FET region, the n-type GaAs layer 307 is selectively removed by dry etching with respect to the n-type AlGaAs layer 304.
Then, as shown in FIG. 4E, the photo resist layer 311b is removed through a step subjecting overall wafer to plasma discharge using oxygen gas in a reaction vessel for generating plasma discharge, such as a barrel type or parallel plate reaction vessel (hereinafter referred to as "oxygen plasma") and a step for implementing water washing process after dipping in a high mixture liquid of dichlorobenzenphenol and alkyl benzene sulfonate at high temperature (120.degree. C.), methyl ethyl ketone and alcohol in high sequential order (hereinafter referred to as "high temperature organic peeling").
Next, as shown in FIG. 4F, Schottky metal to be the gate electrode is deposited over the entire surface. Then, by lithography and RIE technology, gate electrodes 315 and 316 are formed. Subsequently, using a photo resist as a mask, an opening is formed in the insulation layer 310. Then, by a deposition lift method, source electrodes 317 and 319 and drain electrodes 318 and 320 are formed. Thus, the semiconductor device is obtained.
Next, a second example of the fabrication process of the semiconductor device of FIG. 3 will be discussed with reference to FIGS. 5A to 5C.
At first, as shown in FIG. 5A, after epitaxial growth, gate opening formation, side wall insulation layer formation are formed in similar manner to the first fabrication process, the gate opening 314 of the D-type FET region is covered with the photo resist layer 311b. The n-type AlGaAs layer 308 exposed through the gate opening 313 of the E-type FET region is removed by wet etching.
Next, as shown in FIG. 5B, after removing the photo resist layer 311b using methyl ethyl keton, selective dry etching is performed over the entire surface. Then, in the E-type FET region, the n-type GaAs layer 307 as the threshold voltage control layer is removed by selective etching with respect to the n-type AlGaAs layer 304 as the electron supply layer. On the other hand, in the D-type FET region, the n-type AlGaAs layer 308 serves as a mask to stop etching.
Next, as shown in FIG. 5C, similar to the first fabrication process, the gate electrodes 315 and 316, the source electrodes 317 and 318 and the drain electrodes 319 and 320 are formed to obtain the semiconductor device.
However, in the prior art illustrated in FIG. 1 and FIGS. 2A to 2E, when isotropic selective etching is performed simultaneously for the n-type GaAs layer 207 of the E-type FET and the n-type GaAs layer 209 of the D-type FET, the layer thickness of the n-type GaAs layer to be etched are significantly different. Therefore, over etching amount in the FET region having smaller layer thickness, i.e. D-type FET region in the shown example, becomes greater than that region having a larger layer thickness and the side etching amount also becomes greater. Therefore, in the D-type FET having a smaller thickness of the layer to be etched, the gate length becomes large, thus degrading controllability.
Furthermore, during the process step shown in FIG. 2D, namely in anisotropic selective dry etching implemented before formation of the gate electrode, since the layer thickness to be etched is significantly differentiated, the over etching amount in the FET region having smaller layer thickness, i.e. E-type FET region in the shown example, becomes greater. Thus, the etching amount of the n-type AlGaAs layer 204 as the electron supply layer in the E-type FET region becomes large to make Vth of the E-type FET smaller than the desired value, thus causing a degradation of controllability.
On the other hand, in the first fabrication process shown in FIGS. 4A to 4F of the semiconductor device shown in FIG. 3, oxygen plasma and high temperature organic peeling including chlorine are employed for removing the photo resist layer 311b hardened upon selective dry etching of the second n-type GaAs layer 307 in the E-type FET region. Therefore, AlGaAs layer is oxidized by oxygen plasma, and about 5 nm of AlGaAs layer is removed by high temperature organic solvent including chlorine. Accordingly, the AlGaAs layer of the E-type and D-type FETs is reduced. As a result, the desired Vth cannot be obtained, and controllability of Vth can be degraded.
On the other hand, in the second fabrication process illustrated in FIGS. 5A to 5C of the semiconductor device of FIG. 3, while the photo resist is not hardened and thus can be peeled off by methyl ethyl keton, the AlGaAs layer of the D-type FET region is subjected to plasma radiation upon selective dry etching of the overall surface, and the layer thickness is reduced which results in dry etching damage. Moreover, Vth becomes shallow in the D-type FET region. Thus, the difference between Vth of the D-type and E-type FET is not optional, or controllability of Vth of the D-type FET is degraded.